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Design SuperSynth wavetable banks and a supported data-loading path #5

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opened 2026-08-22 16:39:55 +00:00 by peterswimm · 1 comment
peterswimm commented 2026-08-22 16:39:55 +00:00
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Audit finding

src/SuperSynth.cpp currently writes one fixed BRR ramp into emulated SPC700 RAM and records a TODO for wavetable banks or other data-loading methods.

Completion criteria

  • Define the user-facing source/bank model and licensing rules for included audio data.
  • Implement the smallest viable bank/loading path.
  • Document controls, persistence, and failure behavior.
  • Add tests or fixtures for RAM and BRR setup.
## Audit finding `src/SuperSynth.cpp` currently writes one fixed BRR ramp into emulated SPC700 RAM and records a TODO for wavetable banks or other data-loading methods. ## Completion criteria - Define the user-facing source/bank model and licensing rules for included audio data. - Implement the smallest viable bank/loading path. - Document controls, persistence, and failure behavior. - Add tests or fixtures for RAM and BRR setup.
peterswimm commented 2026-08-22 16:40:44 +00:00
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Spelwork tracking: pending wish 86d353c1 under actor peterswimm.

Spelwork tracking: pending wish `86d353c1` under actor `peterswimm`.
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peter-swimm/potatochips#5
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